335 Alternate Device Structures for CMOS

It is widely recognized that CMOS device fabrication in the sub-50 nm regime will put significant pressure on current device designs and fabrication approaches. Several designs for advanced structures have been proposed, and some have promising capabilities and potential to be manufacturable.18-22 Some of these structures include dual-gate designs, where gate electrodes on top and bottom of the

FIGURE 3.5 Schematic diagram of an example vertical field-effect transistor. For this device, the current between the source and drain flows in the vertical direction. The channel material is formed by epitaxial growth, where the channel length (Lc) is controlled by the film thickness rather than by lithography.

FIGURE 3.5 Schematic diagram of an example vertical field-effect transistor. For this device, the current between the source and drain flows in the vertical direction. The channel material is formed by epitaxial growth, where the channel length (Lc) is controlled by the film thickness rather than by lithography.

channel (or surrounding the channel) can increase the current flow by a factor of 2 and reduce the charging time by a similar factor, as compared with the typical single-gate structure. Such devices can be partially depleted or fully depleted, depending on the thickness of the channel layer, applied field, and dielectric thickness used. Many of these devices rely on silicon-on-insulator (SOI) technology, where very thin crystalline silicon layers are formed or transferred onto electrically insulating amorphous dielectric layers. This electrical isolation further reduces capacitance losses in the device, improving device speed.

Another class of devices gaining interest is vertical structures. A schematic of a vertical device is shown in Figure 3.5. In these devices, the source and drain are on top and bottom of the channel region; and the thickness of the channel region is determined relatively easily by controlling the thickness of a deposited layer rather than by lithography. Newly developed thin film deposition approaches, such as atomic layer deposition, capable of highly conformal coverage of high dielectric constant insulators, make these devices more feasible for manufacturing with channel length well below 50 nm.19

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